Experience and skills requirements:

• 5+ years experience, including successful completion of FPGA/ASIC implementations 
• Coding experience in Verilog and VHDL is required.
• Implementation of designs with multiple clock domains is required
• Thorough understanding of appropriate coding styles for FPGAs, and trade-offs for density and speed
• Experience implementing DSP algorithms in RTL is preferred
• Experience with the development of DSP algorithms and models using Matlab is a plus 
• Experience interfacing with ARM or PowerPC etc is preferred

Responsibilities include: 

• Write functional specifications
• Functional partitioning, block diagram, and detailed design spec
• RTL coding of design in Verilog or VHDL
• Develop testbench and verify at the block level
• Synthesis, mapping to target device, and timing closure