Design and develop verification methodologies and SystemC/C++ infrastructure for functional verification of a system-on-a-chip (SOC).

 Successful candidates should have the following competencies / skills:

•  BSCS, BSEE or equivalent and 5+ years experience in development and support of HW verification environments. 
•  Must be able to architect efficient HW verification systems. 
•  Ability to create and execute HW verification plans. 
•  Expert C++ capabilities within Unix/Linux are required. 
•  Must be able to debug C++ and Verilog/VHDL code, write and debug system-level and block-level tests. 
•  Experience with HW design issues is required. 
•  Experience with SystemC modeling and verification is a strong plus.

 Responsibilities:

 Develop and debug C++/SystemC code for functional testbenches and HW exerciser models;  Integrate C++/SystemC verification code into a system-level verification infrastructure and perform both system-level and block-level testing of the product for a tape-out release.
 Evaluate new HW verification requirements as well as test infrastructure feature enhancements.
 Participate in hardware and software cross-functional verification efforts in order to determine tradeoffs and optimizations for HW/SW co-verification.

We offer you a challenging work in a team of professionals, an excellent career growth opportunity, competitive salary depending on experience, pleasant and friendly start-up attitude, and a great opportunity to make a difference in a highly challenging environment.