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SoC Verification Methodology
Preface
Verification methodology used in VeriXiom is proven to be effective with respect to both labor and cost and is based on joint usage of C/C++ and HDLs and extensive code reuse. The verification methodology and code incorporate the following reusable system elements, which are transferable across projects with minimal effort: user interface, verification environment structure, testbench and transactor design, test writing methodology.
The verification system is based on a communication bridge between the verification C/C++ code and HDL languages like VHDL and Verilog.
Our approach to verification provides for:
- reusability of verification code and methodology;
- scalability for any size SoCs;
- hardware/software co-simulation support;
- lower verification costs - both initial costs, incremental cost per user and life cycle support costs.
Verification system overview
Figure shows the general structure of the verification system. The SOC under test (SUT) is described using an HDL language. User tests are written in C/C++, individually compiled and linked to a set of libraries. The workbench libraries contain application routines created to perform specific data manipulations.
Figure: Verification System
The service libraries usually contain routines to support all stages of the verification system development. This includes routines for error reporting, printing different types of debug messages, generating pseudo-random numbers, sorting and shuffling data arrays, handling input and output databases, statistics reporting and simulation control.
The project efficiency layer routines are project dependent and designed to increase the abstraction level of test C/C++ code. The efficiency routines facilitate:
- setting up the project control structures, SUT registers, ports, connections and input/output databases;
- programming the verification system transactors and SUT interfaces.
The transport layer provides for concurrent transactor-based communications between C/C++ and HDL domains. The transport software supports the:
- ability to create/add any type of interface with large data transfers;
- repeatability of hardware simulations;
- scalability and mobility of the verification system;
- migration from unit to system verification, providing high levels of controllability and observability.
The user interface is a set of Make and Perl/Python/Shell scripts to support:
- compiling C/C++ and HDL code;
- building tests;
- passing test parameters;
- interactive and batch simulations;
- regression testing.
The user interface can also include any user-friendly GUI interface for visual support. In the next section the implementation of the testbench design for the verification of telecommunication SoCs is described.
Described verification approach have been used by authors in many successful projects
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