A method to design and test asynchronous sequential circuits (ASCs) based on the micropipeline design style is presented in this paper. According to the proposed scan test approach the combinational block is tested separately by scanning the test vectors in and  shifting the responses out of the state registers.

The micropipeline approach to designing asynchronous VLSI circuits has successfully been used in the AMULET1 microprocessor. A method to design and test micropipelines is presented in this paper. The test strategy is based on the scan test technique.

A new approach to harmonic-balance simulation uses a frequency-domain-extended standardized modeling language to support the use of "black mboxes" in simulations.

AMULET3i is the third generation asynchronous ARMcompatible microprocessor subsystem developed at the University of Manchester. It is internally modular, being based around the MARBLE asynchronous on-chip bus, and is also extensible through the addition of conventional clocked synthesizable peripherals via an on-chip synchronous peripheral bus.

An asynchronous ARM6 microprocessor (AMULET1), designed at the University of Manchester using a two-phase signalling protocol, and the latest release of the AMULET2e embedded controller, implemented using four-phase signalling, have proved the practical feasibility of the micropipeline design approach.

A resurgence of interest in asynchronous VLSI circuits is occurring because of their poten- tial for low power consumption, design flexibility and the absence of the clock skew prob- lem. In this paper, an approach to the design of asynchronous sequential circuits for random pattern testability based on the micropipeline design style is described.

C-elements are used widely in asynchronous VLSI circuits. Fabrication faults in some CMOS C-elements can be undetectable by logic testing. Testable designs of static symmetric and asymmetric C-elements are given in this report which provide for the detection of single line stuck-at and stuck-open faults.

The ever-competitive market pushes semiconductor IC designs to be packaged on larger dies, incorporating more functionality. In order to achieve the 'time-to-market' targets, semiconductor companies incorporate important blocks and cores, developed and verified by other companies, into their chips.

This paper describes problems related to verification of communication systems and demonstrates approach of digital and harmonic balance co-simulation.