Our services

Overview of the Verification Flow

Verixiom services cover all aspects of the hardware verification flow:

Based on customer inputs like the description of input/output interfaces, design specification, performance, application and other requirements, we develop a proposal about the verification methodology, tools, resources, execution strategy, schedule milestones, and other supporting documentation.

After the project review, we develop a verification plan which normally includes a detailed description of

the verification approach and technology
levels of abstraction for modeling
test application and test execution approach
result checking techniques
testbench requirements
verification infrastructure elements
verification tests
regression testing
bug tracking
sign-off/acceptance criteria.

Execution of the Verification plan.
Monitor functional coverage with each regression.
Identification of ways to improve the coverage results in order to reach the acceptance criteria.
Upon reaching the acceptance criteria, final verification results are delivered and documented in accordance with the project acceptance agreement.

Functional Verification Services

Functional verification is an important part of hardware verification. The principal goal of functional verification is to determine whether the design under verification performs according to its intent and implementation requirements. A hardware design can be described at several levels depending on the level of details: architecture and design implementation specifications. Thus, the challenge of functional verification is to prove that the design intent described in the architecture specification is in agreement with the actual design implementation.

Verixiom's approach to functional verification is based on cross verification between design intent (high-level modeling) and implementation models (normally, RTL/Gate-level modeling) and their corresponding specifications. In addition, the design intent model and its corresponding implementation model are dynamically verified during simulation.
Functional verification is considered complete when the acceptance criteria is reached. The most important components of the verification acceptance criteria are:

bug rate distribution during the project execution
functional coverage results
Verilog/VHDL RTL line and conditional coverage data

Though verification is never done, the probability of a fatal design failure can be lowed dramatically if the verification quality is measured and proved qualitatively to satisfy the acceptance criteria.

Model Development Services

In order to prove that Verilog/VHDL RTL implementations of a block, sub-chip, or system-on-a-chip (SOC) correspond to their specifications, we create transaction-level predictor models that are simulated in parallel with their corresponding Verilog/VHDL models. The predictor models are designed to verify the correctness of the RTL designs by comparing RTL responses with the predicted values during simulation runs. In addition, Verixiom develops interface (Bus Functional Model) BFM models to simulate
the behavior of SOC external interfaces.

Some commonly used or industry standard interfaces are modeled and packaged as verification intellectual property (VIP) components. Verixiom has developed a process for the development and verification of its VIPs. For our customers, pre-designed and pre-verified VIPs provide for

a faster SOC verification testbench development and integration
a shorter debug cycle
an ability to find design bugs faster Digital Design Services Besides

an extensive verification experience, Verixiom developed an expertise in hardware design. The competence areas in hardware design include digital signal processing, high speed digital circuit design for telecommunication applications, mixed-mode and RF simulation.